Basic PCB Design Rules Before Your First Fabrication

Most first PCB problems do not come from one dramatic mistake. They come from ordinary layout decisions that looked harmless in the CAD tool. A connector footprint is mirrored. A regulator is placed far from its capacitors. A switching node is routed beside an ADC input. The board passes design rule check, but the exported drill file is wrong. The assembled prototype powers on, then resets as soon as a relay or radio turns on.

That is why PCB design rules should not be treated as a list of fixed dimensions. A rule is only useful when it connects a design input to a physical effect: current, voltage, heat, solder, copper geometry, return path, test access, or manufacturing tolerance. Beginners need simple rules, but they also need rules that survive contact with a real fabricator and a real first-board bring-up.

This article is written for beginners who are ready to send a board out for fabrication and want to avoid the most common avoidable failures. The structure is intentionally rule-based, but each rule includes the reason behind it, the mistake it prevents, and the evidence you should check before release. The goal is not to memorize a universal PCB formula. The goal is to build a board that can be manufactured, assembled, measured, debugged, and improved.

Rule 1 Start With Requirements Before Drawing Traces

A PCB layout begins before the first component is placed. If the design requirements are vague, the layout rules will also be vague. A CAD tool can enforce minimum clearance and trace width, but it cannot know the product voltage, current, enclosure, operating temperature, layer budget, connector access, assembly process, or test strategy unless the designer defines those inputs.

Start with a short layout brief. It does not need to be a formal document, but it should answer the questions that drive board geometry. What is the maximum current on each rail? Which nets have fast edges or controlled-impedance requirements? Which circuits are noise-sensitive? What voltage spacing is safety-related rather than only functional? What parts are fixed by the enclosure? Will the board be hand assembled, SMT assembled, or built with mixed technology? Which signals must be measured during bring-up?

Without those inputs, beginners often copy default CAD rules from a previous project. That may work for a low-voltage LED board, but it can be wrong for a motor driver, a switching regulator, a USB interface, a high-voltage sensor board, or a compact RF product. The rule is simple: define the engineering input before choosing the layout constraint.

Use this early checklist before placement:

Layout input	What to define before routing	What can fail if it is guessed
Board outline	Enclosure edges, connector positions, mounting holes, keepouts, height limits	Connectors do not fit, mounting screws interfere, or assembly access is blocked
Power	Rail voltage, load current, inrush, protection, regulator type, heat source	Voltage drop, overheating, startup failure, or unstable regulation
Signals	Clock edges, buses, analog inputs, differential pairs, RF paths, reset and boot lines	Noise pickup, crosstalk, intermittent communication, or hard-to-debug startup behavior
Fabrication	Layer count, copper weight, board thickness, finish, drill limits, impedance needs	Quote delay, manufacturability issues, or uncontrolled impedance
Assembly	Package pitch, polarity, side of assembly, fiducials, rework access, stencil needs	Misplacement, solder defects, inaccessible parts, or ambiguous assembly data
Test	Test pads, programming access, rail measurement points, ground references	Bring-up becomes guesswork instead of measurement

This requirements-first step is what makes the rest of the rules meaningful. A trace-width rule without current is a guess. A clearance rule without voltage and environment is a guess. A routing rule without return-path context is a guess.

Rule 2 Verify Footprints Before Placement

Footprints are a quiet source of expensive errors. A schematic can be correct while the board is wrong because the physical land pattern does not match the part. Common first-board issues include mirrored connectors, swapped pins on transistors or MOSFETs, missing thermal pads, incorrect hole sizes, wrong pin 1 orientation, and polarity marks that disagree between the silkscreen and the actual component.

Do not treat a downloaded footprint as evidence. Treat it as a draft. Check the manufacturer part number in the BOM, then compare the schematic symbol, package drawing, recommended land pattern, exposed pad, mechanical outline, pin numbering, height, and polarity marking. For connectors, look from the mating side and the board side. Many connector mistakes happen because the designer views the part from the wrong direction.

If a part will be assembled by a supplier, the footprint also needs assembly clarity. The reference designator should be readable. The polarity or pin 1 mark should be visible after placement. The courtyard should leave enough spacing for adjacent components. Exposed thermal pads should match the soldering strategy, especially when via-in-pad, via tenting, filling, or paste-window design is involved.

Electrical rule check and design rule check can help, but they cannot prove that the footprint matches the datasheet. Use this evidence chain before layout:

1. Confirm the manufacturer part number in the BOM.
2. Compare the schematic symbol pin mapping with the datasheet.
3. Compare the footprint pads, holes, outline, and pin 1 mark with the package drawing.
4. Review the 3D model or mechanical view against the enclosure and nearby parts.
5. Check the assembly drawing view for polarity, side, and reference designator clarity.

If any item in that chain disagrees, fix the library before routing. Routing a board around an unverified footprint only makes the eventual correction more painful.

Rule 3 Place Components by Function and Current Flow

Good placement is not about making the board look balanced. It is about reducing conflict before routing starts. A beginner board often becomes difficult because power, analog, digital, connectors, heat sources, and test access were placed as separate objects rather than as a system.

Place fixed mechanical items first: board outline, connectors, mounting holes, switches, displays, LEDs, antennas, heatsinks, and enclosure keepouts. Then place by functional blocks. A useful beginner board might have a power-input area, protection area, regulator area, MCU area, sensor or analog front end, communication interface, driver stage, programming connector, and test access area.

After the blocks are placed, follow current flow. Power should enter, pass through protection or filtering, reach the regulator, feed the load, and return through a path that is visible during layout review. High-current loads should not force return current through a sensitive analog reference. A switching regulator should not be crowded against a crystal or high-impedance sensor input. A connector carrying field wiring should not force fast digital traces into a noisy corner of the board.

This placement-first discipline prevents a common beginner trap: routing everything that fits, then discovering that the most important trace has no clean path left. If the placement makes the power loop long, the return path broken, or the test pads unreachable, routing will not fix the underlying problem.

Before you lock placement, ask these review questions:

• Where does power enter, where does it go, and where does it return?
• Which components generate heat, switching edges, or large current pulses?
• Which pins are high impedance, analog, timing-critical, or noise-sensitive?
• Which connectors, buttons, LEDs, or test pads need human access?
• Which components need rework space during prototype debug?

If the board cannot answer those questions visually, keep working on placement.

Rule 4 Build the Stackup Around Return Paths

A PCB trace is not a wire floating in air. It works with nearby copper, dielectric, and return current. On a two-layer board, the return path may be a bottom-layer ground pour that is interrupted by traces, slots, or narrow necks. On a four-layer board, the return path may be a solid plane next to the signal layer. The difference matters.

Many beginners decide layer count from price alone. Cost matters, but layer count also affects routing density, return-path control, power distribution, EMI risk, and impedance control. A two-layer board can work well for simple low-speed circuits when the ground return is planned carefully. A four-layer board can be easier for compact designs because it can provide a continuous reference plane and a cleaner power distribution path. More layers do not make a board correct by themselves, but the stackup gives the layout its electrical environment.

High-speed behavior is driven by edge rate and interconnect environment, not only by clock frequency. A board with a modest clock can still produce fast transitions that need controlled return paths. When a signal crosses a plane split, changes layers without a nearby return via, passes over a void, or routes around a cut in reference copper, return current detours. That detour increases loop area and can increase ringing, crosstalk, emissions, or susceptibility.

For a beginner, the practical stackup rule is this: route important signals over continuous reference copper, and plan layer changes with nearby ground return vias. Do not route clocks, USB-style interfaces, crystal nets, feedback nodes, or sensitive analog inputs across reference gaps simply because the trace fits. Length matching does not repair a broken return path.

When controlled impedance is required, stackup must be confirmed before final routing. Trace width alone does not define impedance. Dielectric thickness, dielectric constant, copper thickness, solder mask, reference plane, fabrication tolerance, and adjacent copper all matter. If the fabricator will build impedance-controlled boards, give them the target impedance, tolerance requirement, stackup assumption, reference layer, and any coupon or measurement expectation needed for the project.

Rule 5 Route Power and Ground Before Ordinary Signals

Power and ground should be designed before low-risk signal routing. A 5 V input feeding a 3.3 V rail is not just a red trace from one pin to another. Current flows from the connector through protection or filtering, into the regulator, through the output capacitor, into the load, and back through the ground system. The complete loop matters.

For a linear regulator, place the input and output capacitors close to the regulator pins and follow the datasheet layout example. For a switching regulator, the high-current loop, switch node, inductor, diode or synchronous FET path, output capacitor, feedback path, and power ground deserve layout attention before general GPIO. The regulator datasheet and application note should be treated as the first source, because the correct layout depends on topology, package, switching frequency, current, and board stackup.

Check each rail in three ways. First, is the copper wide and short enough for the current and allowed voltage drop? Second, does the return current have a low-impedance path, or is it forced through a narrow neck, connector ground pin, or plane interruption? Third, can the rail be measured near the load during bring-up?

Copper pours can help with resistance and heat spreading, but a pour is not a substitute for a planned current path. A pour with narrow thermal necks, sparse vias, or poor connection to the load may look impressive while doing little useful work. Review the actual current path, not the amount of copper color on the screen.

Rule 6 Set Trace Width Clearance and Via Rules From Evidence

Trace width, spacing, and via size should not come from a default template. They should come from current, voltage, copper thickness, board layer, temperature rise, impedance needs, fabrication limits, and assembly constraints.

One useful anchor is copper weight. One ounce copper is commonly described as about 35 um nominal copper thickness before process variation. That helps a beginner understand why 2 oz copper, inner-layer routing, etching limits, and thermal spreading affect current capacity. It does not mean one trace width safely carries one fixed current on every board. Board thickness is similar. A 1.6 mm rigid board is common, but it is not a rule. Mechanical stiffness, connector fit, impedance, layer count, product height, and fabrication process can change the thickness decision.

Clearance needs the same discipline. For low-voltage learning circuits, functional spacing may be easy to satisfy. For higher voltage, transients, mains-adjacent circuits, harsh environments, or regulated products, clearance and creepage must be routed through the applicable standard and product conditions. A generic web value is not enough because spacing can depend on voltage, pollution degree, material group, coating, altitude, environment, and market requirements.

Rule area	Input data to check	Risk if guessed	Evidence before release
Trace width	Current, copper weight, layer, allowed temperature rise, voltage drop	Hot copper, excessive drop, unreliable connector or via heating	Calculator with assumptions, fabricator limits, prototype temperature measurement
Trace clearance	Working voltage, peak/transient voltage, environment, product category	Arcing, leakage, contamination sensitivity, safety nonconformance	Applicable standard, customer requirement, fabricator DFM review
Vias	Drill size, plating, board thickness, current, signal edge rate	Voltage drop, thermal stress, impedance discontinuity, reliability risk	Fabricator capability, via current/thermal review, SI review where needed
Annular ring	Drill tolerance, pad size, finished hole, registration	Breakout, weak plating margin, fabrication rejection	Fabricator design rules and drill table review
Controlled impedance	Stackup, dielectric, copper, solder mask, reference plane	Wrong impedance, reflections, failed interface margin	Fabricator stackup, field-solver or calculator result, coupon plan where required
Solder mask and paste	Package pitch, pad geometry, stencil approach, finish	Bridging, insufficient solder, solder balls, assembly rework	Assembly supplier DFM feedback and package recommendations

This is where beginner and professional PCB design meet. A beginner can start with conservative default rules for simple boards, but the moment the board carries meaningful current, voltage, fast edges, fine-pitch components, or controlled interfaces, the rules need evidence.

Rule 7 Keep Decoupling Loops Short and Measurable

Many beginner schematics show a row of 0.1 uF capacitors and assume the power problem is solved. A 0.1 uF capacitor is a common starting point, not a universal answer. Decoupling works because a local capacitor supplies transient current while the regulator, planes, package, and bulk capacitance respond over different time ranges. The physical current loop determines how useful the capacitor is.

Place high-frequency decoupling capacitors close to the IC power and ground pins they support. Use short, direct connections. Put vias where they reduce loop inductance rather than where they are visually convenient. If the IC has multiple power domains or pin groups, follow the datasheet guidance for each group instead of placing all capacitors in one neat row.

MLCCs also behave less ideally than the schematic symbol suggests. Effective capacitance can drop with DC bias, and package parasitics affect high-frequency behavior. Beginners do not need a full power-distribution-network simulation for every simple board, but they should understand that capacitor value alone does not define decoupling performance.

Make the decoupling loop visible during layout review. Then make it measurable during bring-up. Place rail test points or reachable vias near important loads. When checking ripple or switching noise, use a short ground connection on the oscilloscope probe; a long ground lead can show probe-loop noise rather than the actual rail behavior. If resets, ADC errors, display flicker, or wireless dropouts correlate with load changes, rail measurement near the IC pins is often more useful than measuring only at the regulator output.

Rule 8 Separate Noisy Sensitive and Fast Sections

Even a beginner board can contain several electrical personalities. A small MCU board may include a switching regulator, crystal, USB connector, I2C sensor, ADC input, relay driver, motor output, LEDs, and programming header. Those nets should not be routed as if they all have the same noise tolerance.

Start by naming the aggressors and victims. Aggressors include switching nodes, motor-drive outputs, relay coils, high-current pulses, fast clocks, RF outputs, and long connector cables. Victims include high-impedance analog inputs, sensor nodes, oscillator pins, feedback pins, reset lines, reference voltages, and low-level measurement circuits. The exact list depends on the product, but the review method stays the same: identify which nets can inject noise and which nets can be disturbed by it.

Switching nodes should be compact while still meeting current and thermal needs. Do not pour unnecessary copper on a high-dV/dt node just because copper is available. Analog inputs should avoid long parallel runs beside clocks, PWM, switching power nodes, or connector lines carrying uncertain external noise. Crystal nets should stay close to the IC and away from large current loops. Differential pairs should see a consistent environment and a continuous reference path before length matching is treated as the main problem.

Use a failure question during review. If this trace picks up noise, what will the user see? Possible answers include ADC offset, communication dropouts, false interrupts, reset events, unstable feedback, motor misbehavior, touch-sensor errors, or EMI trouble. That failure-oriented question is more useful than asking whether the board simply "looks clean."

Rule 9 Design Pads Vias and Thermal Features for Manufacturing

Manufacturing rules are not an afterthought. DRC checks the rules you typed into the CAD tool. DFM checks whether a specific fabrication and assembly process can build the board with margin. A board can pass DRC and still create production questions because the CAD rules do not know the fabricator's current process limits, solder mask registration, drill tolerance, surface finish, panelization plan, stencil process, or inspection method.

Review pads, vias, and thermal features as manufacturing structures. A via in or near a thermal pad can wick solder away unless it is properly filled, capped, tented, or handled in the paste design. A QFN exposed pad may need paste-window control to reduce float and voiding risk. Thermal vias can help move heat into copper planes, but they can also affect soldering if placed without an assembly plan. High-current vias should be treated as arrays with current sharing and thermal behavior, not as decorative holes.

Fine-pitch components need solder mask and paste attention. Narrow solder mask slivers may be difficult to fabricate. Silkscreen over pads can contaminate solderable surfaces or disappear during CAM cleanup. Component-to-edge clearance, connector access, rework space, fiducials, tooling holes, and assembly-side clarity can affect the board long before the circuit is powered.

The professional habit is to ask the fabricator and assembler for their design rules before release. Put practical limits into the CAD rules where possible. For non-standard features, such as controlled impedance, heavy copper, microvias, blind or buried vias, filled vias, via-in-pad, gold fingers, castellations, special laminates, high-voltage spacing, or unusual panelization, state the requirement in the fabrication or assembly notes and get confirmation before production.

Rule 10 Make Silkscreen Polarity and Assembly Intent Clear

Silkscreen is not decoration. It is a communication layer for assembly, inspection, test, rework, and field service. A board with technically correct copper can still create mistakes if the silkscreen hides polarity, uses ambiguous connector labels, places reference designators under components, or marks pin 1 in a way that conflicts with the package.

At minimum, mark pin 1 or polarity for ICs, diodes, LEDs, electrolytic capacitors, polarized connectors, batteries, and programming headers. Label connectors by function, not only by reference designator, when the product needs service or lab use. Mark voltage rails and ground test points where useful. Keep text off solderable pads, mounting holes, and areas likely to be removed or covered.

Reference designators should support inspection. For dense boards, this may mean placing designators just outside the component area and keeping orientation consistent enough that an assembler can locate parts quickly. On prototypes, readable labels for reset, boot, SWD/JTAG, UART, I2C, power input, and critical test points can save hours during bring-up.

Silkscreen also needs a release check. Open the manufacturing output and confirm that the silkscreen layer did not shift, overlap pads, disappear under components, or become unreadable after fabrication minimum line-width cleanup. The CAD view is not enough because CAM output can differ from what the designer expected.

Rule 11 Use DRC DFM and Gerber Review as Separate Gates

DRC, DFM, and Gerber review answer different questions. DRC asks whether the board violates the rules in the CAD file. DFM asks whether the fabricator and assembler can build the board with process margin. Gerber and drill review asks whether the exported manufacturing data actually represents the intended design.

Beginners often stop at DRC because it feels like an approval. It is not. If the CAD rules are incomplete, DRC can pass a board with inadequate spacing, missing fabrication notes, ambiguous assembly data, or poor test access. If the export settings are wrong, the CAD layout can be correct while the Gerber package is wrong.

Before release, open the exported data in an independent viewer. Check copper layers, solder mask openings, paste layers, silkscreen, board outline, slots, plated and non-plated holes, drill file alignment, polarity marks, and reference designators. If the board uses controlled impedance, special materials, nonstandard thickness, heavy copper, backdrilling, via filling, or a particular finish, confirm that the fabrication notes communicate the requirement.

Gerber remains a common PCB manufacturing data format, and Ucamco maintains the Gerber format specification. However, Gerber files alone do not communicate every piece of engineering intent. A complete release package may also need drill files, stackup, fabrication drawing, assembly drawing, BOM, pick-and-place data, revision notes, test requirements, special process notes, and acceptance criteria.

Rule 12 Leave Test Access for First Board Bring-Up

The first revision of a PCB is not only a product prototype. It is also a measurement platform. If the board has no test access, a simple fault becomes a long debug session. A beginner board should assume that some rail, reset line, clock, boot pin, or communication bus may need to be measured.

Add accessible ground, input voltage, regulator outputs, MCU supply, reset, enable pins, boot-mode pins, programming signals, important buses, and key analog nodes. Test pads do not need to turn every prototype into a full in-circuit-test fixture, but they should make bring-up possible without balancing a probe on a fine-pitch IC pin. Leave enough room for the probe, clip, pogo pin, or wire that will actually be used.

Test access also improves the second revision. If a wireless module causes the regulator to droop during transmit, you need a place to measure the rail near the load. If I2C fails, you need access to SDA, SCL, and a ground reference. If the MCU does not start, you need reset, boot, clock, power, and programming evidence. Without those points, debug turns into inference.

When the first board requires jumpers, cut traces, resistor changes, or firmware boot-mode changes, record them immediately. Update the schematic, layout, BOM, and release notes. Many second-revision failures happen because prototype fixes were understood in the lab but not captured in the design files.

Rule 13 Route Standards Through Their Correct Scope

IPC and other professional standards matter, but they are not blanket proof that a board is correct. The IPC standards ecosystem covers different parts of the electronics life cycle, including design, bare-board fabrication, assembly acceptability, and related processes. A design note that casually claims an IPC result is not useful unless it identifies the applicable document, revision, class, scope, inspection method, and customer requirement.

For example, IPC-A-610 is commonly associated with assembled board acceptability. That does not make it a bare-board routing rule. IPC-6012 addresses performance requirements for rigid printed boards. That does not prove the assembled solder joints meet the required workmanship class. IPC-7351 land pattern guidance is different from a regulator datasheet layout requirement. IPC-2221 family design guidance is different from a product-specific high-voltage safety requirement.

Use standards as routing points, not as decoration. If a claim involves safety spacing, IPC class, workmanship acceptability, medical, automotive, aerospace, EMC, ESD control, environmental compliance, or reliability qualification, the article or drawing should point to the correct evidence path. For many beginner boards, the practical release evidence will be the component datasheet, fabricator design rules, assembly DFM feedback, DRC, Gerber review, and staged prototype measurement. For regulated or high-reliability products, the evidence requirement is much higher.

This standard-scope discipline protects beginners from overconfidence. A board can be neat, functional, and professionally laid out without being certified, qualified, or compliant for a regulated market. Do not claim more than the evidence supports.

Rule 14 Bring Up the Board in Stages

The design is not finished when the files are uploaded. First-board bring-up is part of PCB design because it verifies whether the physical implementation matches the electrical intent. The riskiest bring-up method is to connect the full supply, attach every peripheral, load the firmware, and hope the board runs.

Use staged bring-up. Start with visual inspection. Check orientation, missing parts, solder bridges, damaged connectors, and obvious assembly issues. Measure resistance on main rails before applying power. Use a current-limited bench supply for the first power-up. Bring up one rail or section at a time when the design allows it. Confirm input current, regulator output, MCU supply, reset state, clock, boot pins, and programming interface before connecting high-current loads or external equipment.

A multimeter is useful for static resistance and voltage checks. An oscilloscope is needed for ripple, reset timing, clocks, communication waveforms, and fast events. A thermal camera or IR thermometer can reveal unexpected heating, but temperature must be interpreted with load condition, package, airflow, ambient temperature, and measurement location.

The key is to test the failure mechanism, not merely the symptom. If a rail droops during motor startup, measure the rail at the load and at the regulator. If a communication bus fails, check waveform amplitude, timing, pullups, ground reference, and connector wiring. If a regulator is hot, estimate power dissipation and review copper area, airflow, load current, and package thermal limits. Bring-up should create evidence for the next design decision.

Rule 15 Know When Beginner Rules Are No Longer Enough

The rules above are a strong starting point, but some boards need specialist review. High-voltage boards need standards-based creepage and clearance decisions. High-current boards need connector, copper, via, thermal, and solder-joint review. High-speed boards need stackup, return-path, impedance, via-stub, crosstalk, and measurement planning. RF boards need layout, material, antenna, and enclosure review. Fine-pitch BGA or HDI boards need fabrication and assembly planning before placement is final.

The same applies to medical, automotive, aerospace, industrial safety, and other regulated products. A working prototype does not prove compliance, reliability, or production readiness. It only proves that a specific sample worked under the conditions tested. The design still needs the applicable standards, customer requirements, risk analysis, test plan, manufacturing controls, and acceptance criteria.

A good beginner habit is to flag uncertainty early. If a rule depends on voltage spacing, impedance tolerance, thermal margin, EMC behavior, reliability life, or inspection class, write down what evidence is missing. Then get the datasheet, fabricator guidance, assembly DFM feedback, test data, or standards review needed to close the gap.

Conclusion

Basic PCB design rules are not shortcuts around engineering judgment. They are a practical order of work. Define the requirements, verify footprints, place by function, plan stackup and return paths, route power before ordinary signals, set widths and clearances from evidence, design for manufacturing, leave test access, review exported files, and bring up the first board in stages.

If you follow that sequence, your first PCB may still need a second revision. That is normal. The difference is that the board will be easier to inspect, easier to assemble, easier to measure, and easier to improve. A good first PCB is not one that pretends every risk is solved. It is one that leaves enough evidence to solve the next problem correctly.

FAQ

Should beginners start with a two-layer or four-layer PCB?

Two-layer boards are suitable for many low-speed learning projects when ground return is planned carefully. Four-layer boards can make return paths, power distribution, and compact routing easier. The decision should come from circuit speed, current, noise sensitivity, board size, cost, and manufacturability rather than layer count alone.

Is autorouting useful for beginner PCB design?

Autorouting can help with noncritical low-speed nets after placement and critical routing decisions are complete. It should not be trusted for regulator loops, decoupling paths, crystals, feedback traces, sensitive analog inputs, differential interfaces, or controlled-impedance routing without review.

Is a wider PCB trace better?

A power trace needs enough width for current, voltage drop, temperature rise, and manufacturing margin. Wider copper is not automatically better for every net because it can affect routing density, impedance, soldering balance, and component escape. Choose width from the actual current, copper thickness, layer, temperature target, and board rules.

Why can a correct schematic still produce a failing PCB?

The schematic proves connectivity, not physical implementation. A board can fail because of wrong footprints, poor placement, long power loops, broken return paths, weak decoupling, ambiguous assembly data, solder defects, missing test access, or export-file errors.

Do Gerber files need independent review?

Yes. The CAD layout view and exported manufacturing files are not the same thing. Independent Gerber and drill review can catch missing layers, board-outline errors, drill alignment issues, solder mask problems, silkscreen over pads, polarity mistakes, and incorrect export settings before the supplier receives the package.

Do beginners need IPC standards before designing a PCB?

For simple learning boards, beginners usually start with datasheets, fabricator rules, DRC, DFM feedback, and careful measurement. IPC standards become important when the project needs defined design guidance, fabrication requirements, assembly acceptability, inspection class, or customer-controlled workmanship criteria. Do not claim IPC compliance without the correct standard, revision, scope, and evidence.